The present invention relates generally to logic circuits and, more particularly, to clocked full-rail differential logic circuits.
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG. 3(c), in xe2x80x9cHIGH SPEED CMOS DESIGN STYLESxe2x80x9d by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1 shows a prior art full-rail differential logic circuit 100 similar to that discussed in the Bernstein et al. reference. As seen in FIG. 1, prior art full-rail differential logic circuit 100 included six transistors: PFET 105, PFET 107, NFET 109, PFET 115, PFET 117 and NFET 121. Prior art full-rail differential logic circuit 100 also included: differential logic 123 with inputs 151 and 153; out terminal 111; and outBar terminal 113. Prior art full-rail differential logic circuit 100 is activated from a delayed clock signal CLKA. As shown in FIG. 1, signal CLKA was supplied to: gate 116 of PFET 115; gate 118 of PFET 117; gate 129 of NFET 109; and gate 122 of NFET 121.
Prior art full-rail differential logic circuit 100 worked reasonably well, however, during the evaluation phase, prior art full-rail differential logic circuit 100 drew excess power unnecessarily as the relevant inputs, 151 or 153, to logic network 123 were transitioning low to shut off the path of one of the complementary output terminals, out terminal 111 or outBar terminal 113, to ground. The high output terminal, out terminal 111 or outBar terminal 113, therefore experienced a xe2x80x9cdipxe2x80x9d during the transition when the inputs 151 or 153 switched from high to low and a short circuit current, or crossbar current, path was established from Vdd 102 to ground. This xe2x80x9cdipxe2x80x9d was undesirable and resulted in significant power being wasted.
In addition, the structure of prior art full-rail differential logic circuit 100 was particularly susceptible to noise. This problem was extremely undesirable, and damaging, since, typically, multiple prior art full-rail differential logic circuits 100 were cascaded in long chains (not shown) of prior art full-rail differential logic circuits 100. In these chain configurations, the susceptibility of prior art full-rail differential logic circuit 100 to noise meant that each successive stage of the chain contributed additional noise and was even more adversely affected by the noise than the previous stage. Consequently, a few stages into a chain of prior art full-rail differential logic circuits 100, noise became the dominant factor in the chain.
What is needed is a full-rail differential logic circuit that does not experience the large xe2x80x9cdipxe2x80x9d experienced by prior art full-rail differential logic circuit 100 and is therefore more power efficient. In addition, it is desirable to have a full-rail differential logic circuit that is more resistant to noise than prior art full-rail differential logic circuit 100.
According to the present invention, clocked full-rail differential logic circuits include shut-off devices to minimize the xe2x80x9cdipxe2x80x9d at the high output node that was associated with prior art clocked full-rail differential logic circuits. The shut-off device of the invention isolates the high output terminal immediately from the input terminals when the complementary output terminal is pulled to ground. Consequently, according to the present invention, the window period, or path, for the short circuit current, or crossbar current, is significantly decreased and power is saved.
In addition, since clocked full-rail differential logic circuits with shut-off include a shut-off device, the high output terminal is isolated from the input terminals and the noise immunity of the clocked full-rail differential logic circuits with shut-off of the invention is significantly better than prior art clocked full-rail differential logic circuits because noise on the input terminal does not affect the high output terminal after evaluation. Consequently, the clocked full-rail differential logic circuits with shut-off of the invention are better suited for application in cascaded chains.
As discussed above, the clocked full-rail differential logic circuits with shut-off of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked full-rail differential logic circuits with shut-off of the invention are cascaded together, the advantages of the clocked full-rail differential logic circuits with shut-off of the invention are particularly evident and the gains in terms of noise immunity, power efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of clocked full-rail differential logic circuits with shut-off. The chain includes a first clocked full-rail differential logic circuit with shut-off. The first clocked full-rail differential logic circuit with shut-off includes: a first clocked full-rail differential logic circuit with shut-off clock input terminal; at least one first clocked full-rail differential logic circuit with shut-off data input terminal; and at least one first clocked full-rail differential logic circuit with shut-off data output terminal.
The cascaded chain also includes a second clocked full-rail differential logic circuit with shut-off. The second clocked full-rail differential logic circuit with shut-off includes: a second clocked full-rail differential logic circuit with shut-off clock input terminal; at least one second clocked full-rail differential logic circuit with shut-off data input terminal; and at least one second clocked full-rail differential logic circuit with shut-off data output terminal.
According to the invention, the at least one first clocked full-rail differential logic circuit with shut-off data output terminal is coupled to the at least one second clocked full-rail differential logic circuit with shut-off data input terminal to form the chain. According to the invention, a first clock signal is coupled to the first clocked full-rail differential logic circuit with shut-off clock input terminal and a second clock signal is coupled to the second clocked full-rail differential logic circuit with shut-off clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first clocked full-rail differential logic circuit with shut-off clock input terminal and the second clocked full-rail differential logic circuit with shut-off clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a clocked full-rail differential logic circuit with shut-off that includes a clocked full-rail differential logic circuit with shut-off out terminal and a clocked full-rail differential logic circuit with shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a first node, the first node is coupled to a first supply voltage.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a first transistor, the first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first node is coupled to the first transistor first flow electrode and the first transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off out terminal. The first transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first node is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor control electrode is coupled to the third transistor first flow electrode and the clocked full-rail differential logic circuit with shut-off outBar terminal. The second transistor control electrode is coupled to the third transistor second flow electrode and the clocked full-rail differential logic circuit with shut-off out terminal. The third transistor control electrode is coupled to a clock signal CLKA.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The first node is coupled to the fourth transistor first flow electrode and the fourth transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off out terminal. The fourth transistor control electrode is coupled to the clock signal CLKA. The fourth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The first node is coupled to the fifth transistor first flow electrode and the fifth transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off outBar terminal. The fifth transistor control electrode is coupled to the clock signal CLKA. The fifth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a shut-off device coupled between the clocked full-rail differential logic circuit with shut-off out terminal and the clocked full-rail differential logic circuit with shut-off outBar terminal and the logic network out terminal and logic network outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off shut-off device includes a sixth transistor, the sixth transistor including a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode. The fourth transistor second flow electrode is coupled to the sixth transistor first flow electrode. The sixth transistor second flow electrode is coupled to the logic network out terminal. The sixth transistor control electrode is coupled to the third transistor first flow electrode and the clocked full-rail differential logic circuit with shut-off outbar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off shut-off device also includes a seventh transistor, the seventh transistor including a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode. The fifth transistor second flow electrode is coupled to the seventh transistor first flow electrode. The seventh transistor second flow electrode is coupled to the logic network outBar terminal. The seventh transistor control electrode is coupled to the third transistor second flow electrode and the clocked full-rail differential logic circuit with shut-off out terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a logic network, the logic network including at least one logic network input terminal, a logic network out terminal and a logic network outBar terminal. The logic network out terminal is coupled to the clocked full-rail differential logic circuit with shut-off out terminal and the logic network outbar terminal is coupled to the clocked full-rail differential logic circuit with shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a eighth transistor, the eighth transistor including a eighth transistor first flow electrode, a eighth transistor second flow electrode and a eighth transistor control electrode. The eighth transistor first flow electrode is coupled to the logic network. The eighth transistor control electrode is coupled to the clock signal CLKA. The eighth transistor second flow electrode is coupled to the second supply voltage.
The present invention provides a full-rail differential logic circuit with shut-off that does not experience the large xe2x80x9cdipxe2x80x9d experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.